1. Field of the Invention
The present invention relates to a signal output circuit included in a bus driving integrated circuit (bus driving IC) and, more particularly, to a tristate type Bi-CMOS signal output circuit included in a hybrid Bi-CMOS integrated circuit of a bipolar transistor and a complementary insulating gate field effect transistor.
2. Description of the Related Art
Generally, a plurality of bus driving integrated circuits includes respective tristate type Bi-CMOS signal output circuits, and the output terminals of the signal output circuits are connected in common to a bus line. FIG. 1 shows bus driving integrated circuits 10 each having Bi-MOS signal output circuit 11. The output terminals of signal output circuits 11 are connected in common to bus line 12. Each of circuits 11 outputs a signal which is high or low in transistor-transistor-logic (TTL) level and its output is rendered in a high-impedance state, and causes a CMOS transistor to make a bipolar transistor at an output stage conductive.
FIG. 2 illustrates a conventional tristate type signal output circuit comprising bipolar output stage 31 and MOS output drive control circuit 32.
In bipolar output stage 31, NPN transistor Q1 for pulling up an output signal and Schottky barrier type NPN transistor Q2 for pulling down an output signal are connected, in a totem pole configuration, between a node of power supply potential VCC and that of ground potential GND, and the connecting point of NPN transistors Q1 and Q2 is connected to output terminal 33. Schottky diode D1 and resistor R1 are connected in series between the node of power supply potential VCC and the collector of NPN transistor Q1. The collector and base of NPN transistor Q1 are connected to the collector and emitter of NPN transistor Q3, respectively, and NPN transistors Q1 and Q3 are Darlington-connected. Resistor R2 is connected between the base and emitter of NPN transistor Q1.
In MOS output drive control circuit 32, P-channel MOS transistor P1, resistor R3, N-channel MOS transistors N1 and N2, and pull-down circuit PD are connected in series between the node of power supply potential VCC and ground GND, N-channel MOS transistor N3 is connected between the base of NPN transistor Q1 and ground GND, and N-channel MOS transistor N4 is connected between the base of transistor Q2 and ground GND. The gate of N-channel transistor N1 is supplied with input signal IN, the gate of N-channel transistor N2 is supplied with output enable signal EN, and the gates of P-channel transistor P1, N-channel transistor N3, and N-channel transistor N4 are supplied with inverted signal EN of output enable signal EN. The connecting point of resistor R3 and N-channel transistor N1 is connected to the base of NPN transistor Q3, and the connecting point of N-channel transistor N2 and pull-down circuit PD is connected to the base of NPN transistor Q2.
Schottky diode D2 is connected between the base of NPN transistor Q1 and the drain of N-channel transistor N1, and Schottky diode D3 is connected between output terminal 33 and the drain of N-channel transistor N1.
An operation of the foregoing signal output circuit will be described.
When output enable signal EN is at a high level and inverted signal EN is at a low level, P-channel transistor P1 and N-channel transistor N2 are turned on and N-channel transistors N3 and N4 are turned off. The signal output circuit thus becomes active.
In this active state, when input signal IN is low in CMOS level, N-channel transistor N1 is turned off. NPN transistor Q3 is thus supplied with a base current from the node of power supply potential VCC through P-channel transistor P1 and resistor R3 and turned on. NPN transistor Q1 is also turned on. NPN transistor Q2 is turned off by discharging electric charges from its base by pull-down circuit PD. A current thus flows from the node of power supply potential VCC to output terminal 33 through Schottky diode D1, resistor R1 and NPN transistor Q1, and thus output signal OUT is set high in TTL level. Since diodes D2 and D3 are then in an off-state, they do not adversely affect a circuit operation.
If input signal IN is high in CMOS level, N-channel transistor N1 is turned on. NPN transistor Q2 is thus supplied with a base current from the node of power supply potential VCC through P-channel transistor P1 and N-channel transistors N1 and N2, and supplied with a base current from output terminal 33 through diode D3 and N-channel transistors N1 and N2. NPN transistor Q2 is therefore turned on. If N-channel transistor N1 is turned on, electric charges are pulled out from the base of N-channel transistor Q3 through N-channel transistors N1 and N2 and pull-down circuit PD, and NPN transistor Q3 is turned off. NPN transistor Q1 is turned off by discharging electric charges from its base by diode D2. The potentials of both ends of resistor R2 are equalized by diodes D2 and D3 and thus transistor Q1 is reliably turned off. The charges of output terminal 33 are supplied to the ground through NPN transistor Q2 and output signal OUT is set at zero in TTL level.
On the contrary, when output enable signal EN is at a low level and its inverted signal EN is at a high level, N-channel transistors N1 and N2 are turned off and N-channel transistors N3 and N4 are turned on. The signal output circuit thus becomes inactive. In other words, NPN transistor Q3, NPN transistor Q1 for pulling up an output signal, and NPN transistor Q2 for pulling down an output signal are turned off, resulting in a high-impedance output state.
Schottky diode D1 is inserted in the signal output circuit shown in FIG. 2 for the following reason.
When the output terminals of a plurality of bus driving integrated circuits each including the signal output circuit shown in FIG. 2 are connected to a common bus line as illustrated in FIG. 1, some of the bus driving integrated circuits are selectively rendered in a non-operating state. Power supply potential VCC is not applied to VCC power supply lines of signal output circuits of the integrated circuits in the non-operating state. Since signals are supplied from the other integrated circuits in an operating state to the bus line, a current may flow from the bus line to the node of power supply potential VCC through output terminal 33, resistor R2, the base and collector of NPN transistor Q1 and resistor R1 in the integrated circuits in the nonoperating state. The current path is however cut off by Schottky diode D1 and therefore the current does not adversely affect the signals on the bus line.
If Schottky diode D1 and resistor R1 are inserted in the signal output circuit as shown in FIG. 2, the collector voltage of NPN transistor Q3 is lowered more than the base voltage thereof by dropping the voltages of diode D1 and resistor R1 when a high-level signal is output from terminal 33. The capability of outputting a current from NPN transistor Q1 is thus reduced, and static characteristics of output current and output voltage are deteriorated. For example, if output current of 24 mA is desired when VCC is 5 V, an output voltage is made much lower than a prescribed voltage.